In a finished Liquid Crystal Flat Panel, a thin layer of liquid crystal (LC) material is disposed between two sheets of glass. On one sheet of glass, a two-dimensional array of electrodes has been patterned. Each electrode may be on the order of 100 microns in size and can have a unique voltage applied to it via multiplexing transistors positioned along the edge of the panel. In a finished product, the electric field created by each individual electrode couples into the LC material and modulates the amount of transmitted light in that pixelated region. This effect when taken in aggregate across the entire 2-D array results in a visible image on the flat-panel.
A significant part of the manufacturing cost associated with LCD panels occurs when the LC material is injected between the upper and lower glass plates. It is therefore important to identify and correct any image quality problems prior to this manufacturing step. The problem with inspecting LCD panels prior to deposition of the liquid crystal (LC) material is that without LC material, there is no visible image available to inspect. Prior to deposition of LC material, the only signal present at a given pixel is the electric field generated by the voltage on that pixel (assuming no physical contact is made with the pixels).
To overcome this limitation, Photon Dynamics developed a floating modulator which, in part, includes a relatively large piece of optically flat glass with a thin layer of LC material formed on its surface, as shown in FIG. 1A.
To inspect the patterned glass plate 10, modulator 15 is physically moved over a region 20 to be inspected and then lowered to within a few microns of the flat-panel's surface, as shown in FIG. 1B. The small air gap 25 between the flat-panel electrodes 30 and the LC modulator 15 allows the electric field from each pixel electrode 30 on the patterned glass plate 10 to couple to modulator 15 to create a temporary visible display of the panel. This visible display is subsequently captured by camera 35 for identification of defects. After inspecting region 20, modulator 15 is lifted and moved to another region on the panel and the process is repeated. Through this step-and-repeat process, the entire LC panel can be inspected for defects. As shown in FIGS. 1A and 1B, LC modulator 15 is shown as including, an LC material 45 and a flat glass 50.
There is a growing need to increase the inspection speed. Inspecting an LCD panel at high speeds using the modulator described above poses technical challenges. For example, the need to physically lift the modulator (which may weigh several pounds) from its present site, move it to the next site and then lower it in preparation for the next inspection operation affects the system throughput.
Moreover, with the modulator described above, the visible image created on the thin LCD layer is obtained by reflecting light from the surface of the LC material. The LC material acts a scattering medium in its off-state and a transmissive medium in the on-state. This typically results in the generation of a DC-component of light modulated with a relatively small mount of information. To camera 35, this means that the imager must be able to handle a relatively large signal (for the DC component) even though the signal containing the information is relatively weak. Furthermore, the relatively large DC-component of light component may carry a correspondingly large amount of shot noise which needs to be overcome to enable one to reproduce the flat-panel defect data. Furthermore, presently known modulators do not readily lend themselves directly to a continuous, linear scanning.
Non-contact capacitive coupling techniques have been developed to test LCD flat panel arrays. In accordance with one such known method, an electrically floating (open-circuited) conductive plate or a diffusion region is brought into close proximity of the LCD panel. This causes the voltage on the LCD pixel to capacitively couple to the floating plate, thereby causing its voltage to vary in proportion to the ratio of the air-gap capacitance to the parasitic capacitances (plate to substrate as well as plate to surrounding circuitry). This voltage change can then be buffered and supplied off-chip to be measured. FIG. 2 shows a two-dimensional array 60 of sensors that may be capacitively coupled to test an LCD panel. Such two-dimensional arrays 60 suffer from a number of disadvantages.
First, such two-dimensional arrays require step-and-repeat movements, thus lowering the testing throughput. Second, the parasitic capacitances of such arrays are relatively large which may result in poor sensitivity. Furthermore, since many of the parasitic capacitances are non-linear (especially when diffusions regions are used) the sensor itself behaves nonlinearly. Moreover, in such two-dimensional arrays, the read-out addressing lines which select which pixel values are sent off-chip, have relatively larger parasitic capacitances.
As is shown in FIG. 2, array 60 is adapted to include both horizontal address lines X and vertical address lines Y running through each pixel element. The distance between these addressing lines and the floating plate will typically be less than the distance from the detector chip to the LCD panel. Therefore, the amount of addressing crosstalk seen in the output data is often relatively large. Furthermore, when testing, e.g., a 40 microns×40 microns per pixel element using two-dimensional array 60, it is required that the sensing circuitry and the sensing electrode (floating plate) for each pixel fit within substantially the same, e.g., 40×40 microns2 area. The area limitation imposed by the horizontal and vertical dimensions of any given pixel prevents the development and use of complex sensing circuitry on two-dimensional arrays. Accordingly, the two-dimensional arrays are forced to use simple sensing circuitry that may not be effective.
FIG. 3 shows a passive conductive plate 205 positioned in close proximity of an LCD pixel electrode 210 to sense the voltage on LCD pixel electrode 210, as known in the prior art. The LCD pixel electrode 210 and the opposing passive electrode 205 form a simple parallel plate capacitor having a capacitance defined by εA/D, where ε is the dielectric constant of the material between the plates, A is the plate area and D is the separation distance between the plates. The degree to which the LCD voltage is coupled to the opposing electrode is determined by the ratio of the parallel plate capacitance defined by plates 205, 210, to the other parasitic capacitances, such as C1 and C2, among others. The larger these parasitic capacitances, the smaller the size of the coupled voltage. Moreover, many of the parasitic capacitance are non-linear and result in a non-linear response in the coupling characteristic. With the exception of reset transistor 230 which periodically resets the passive electrode 205 to a known DC level Vreset, electrode 205 is floating or passive during the sensing process. As is shown, transistor 230 has a source terminal coupled to sensing electrode 205, a gate terminal receiving reset clock signal reset_clk, and a drain terminal coupled to the reset biasing voltage Vreset.
While simple to implement, there are numerous disadvantages to the prior art sensing technique shown in FIG. 3. First, since the passive electrode 205 is floating, its voltage changes as the LCD pixel voltage coupled thereto via plate 210 varies. Accordingly, the parasitic capacitance C1 and C2 directly impact the coupling sensitivity. Second, since the load resistor 220 is adapted to provide gain, the apparent capacitance seen at C1, which is the parasitic capacitance between the gate and drain of transistor 215, is multiplied by this gain, due to the well-known Miller gain effect. This will further reduce detection sensitivity. Third, any noise on the power supply Vdd will couple directly into the output signal Output. Fourth, any variations in the gain of transistor 215 due to aging, temperature or processing directly impacts the output signal quality. Fifth, the multiplication effect of the capacitance C1 reduces the bandwidth of the gain stage provided by transistor 215. Sixth, since the parasitic capacitances are predominantly junction capacitances, the voltage coupling is non-linear. Seventh, the circuit output is limited to a binary logic state, and detection depends on a time-varying change in voltage in the LCD pixel elements during the sensing process.
Active matrix organic light emitting diode (AMOLED) displays require backplanes made with either amorphous or polycrystalline-silicon thin film transistors (TFT). Polycrystalline silicon displays require fabrication using low temperature processes (LTPS) in order to avoid damage to glass and especially flexible (e.g. plastic) substrates. The fabrication of AMOLED backplanes using LTPS can be quite complex requiring as many as, for example, 10 mask steps with precision control requirements. This has been identified as a potential challenge for low cost, high yield manufacturing of large scale AMOLED displays. The fabrication of AMOLED displays using amorphous Si backplanes may require fewer mask steps, but is nearly as challenging. As AMOLED displays become larger, the need for inspection and yield management becomes more critical. Efforts are underway to improve these processes. However, there has been less focus on the development of AMOLED inspection tools, even though they offer the dual promise of more efficient convergence on process development as well as improved yield and lowered cost in AMOLED manufacturing—by capturing killer defects early in the fabrication cycle. As AMOLED displays grow in size and value for the monitor and TV markets, the need for inspections tools will become critical.
One conventional method of inspecting OLED display is to optically inspect the backplanes. FIG. 4 shows an x-y array 400 of pads adapted to receive OLEDs 402. Each OLED 402ij. pad is coupled via an associated transistor 420ij to a data line and to a gate line, where index i refers to the row and index j refers to the column in which the OLED pad 402ij is disposed. Three such data lines, 406, 408, and 410 are shown, and four such gate lines 412, 414, 416, and 418 are shown. For example, OLED pad 40211 is shown as being coupled to data line 406 and to gate line 416 via transistor 42011. Optical testing does not provide functional information on the pixels.